Layout Engineer
Job Description:
The candidate will have the unique opportunity to perform challenging physical layer mask design for high-speed and high-performance Analog/Mixed-signal ICs using today’s state-of-the art deep submicron CMOS technologies. The layout needs to be carefully crafted considering device matching, process gradient effects, timing requirement, noise isolation, and other analog related concerns to deliver the maximum performance.
The candidate will work closely with world-class design engineers to go through different phases of the IC development including block level layout, floor planning, integration, verification, and the tape-out process. Proper training will be provided to bring the candidate to expand technical skills and to bring products successfully.
Qualifications:
BSEE REQUIRED
No relocation assistance is available for this position at this time.
The ideal candidate must work well in a team environment with excellent communication skills. Also, good knowledge on Unix and IC development CAD tools such as Cadence, Magic, Laker, Calibre, etc, and the course work on circuits and device physics are big pluses.
Salary: Open
When to apply:
Now
How to apply:
Please e-mail resume to Tamar Woodbury at tamarw@marvell.com.
